Five stations share the clock.
Does a pipeline finish an instruction faster?
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Does a pipeline finish an instruction faster?
Fit the five pipeline stations.
Five stations overlap different instructions. One instruction still takes five clocks without a hazard, but a six-instruction batch can finish in ten clocks. Dependencies insert bubbles unless forwarding supplies the result. A load needs an extra clock; a taken branch discards younger work rather than retiring it.
Deterministic five-stage in-order teaching pipeline: IF, ID, EX, MEM, WB. Program is producer, dependent ADD, branch, two younger ADDs, target ADD. Branch resolves at the end of EX. Completion is counted on entry to WB. Full forwarding includes WB-to-ID visibility; an immediately used load stalls once. No caches, exceptions, speculation or measured CPU timing.
Retire all six instructions in ten clocks with forwarding and no taken branch.
Compare pipeline throughput with dependencies and hazards.